NTE4081B integrated circuit cmos, quad 2 ? input and gate description: the NTE4081B is a quad 2 ? input and gate device is a 14 ? lead dip type package constructed with p ? channel and n ? channel enhancement mode devices in a single monolithic structure. these complementary mos logic gates find primary use where low power dissipation and/or high noise immunity is desired. features: supply voltage range: 3vdc to 18vdc all outputs buffered capable of driving two low ? power ttl loads or one low ? power schottky ttl load over the rated temperature range triple diode protection on all inputs absolute maximum ratings: (voltages referenced to v ss , note 1) dc supply voltage, v dd ? 0.5 to +18.0v .................................................. input voltage (dc or transient), v in ? 0.5 to v dd to +0.5v .................................... output voltage (dc or transient), v out ? 0.5 to v dd to +0.5v ................................. input current (dc or transient, per pin), i in 10ma ......................................... output current (dc or transient, per pin), i out 10ma ...................................... power dissipation (per package), p d 500mw ............................................. temperature derating (from +65 to +125 c) ? 7.0mw/ c ............................. storage temperature, t stg ? 65 to +150 c ................................................. lead temperature (during soldering, 8sec max), t l +260 c ................................. note 1. maximum ratings are those values beyond which damage to the device may occur.
electrical characteristics: (voltages referenced to v ss , note 2) parameter symbol v dd vdc ? 55 c +25 c +125 c unit min max min typ max min max output voltage ?0? level v ol 5.0 ? 0.05 ? 0 0.05 ? 0.05 vdc v in = v dd or 0 10 ? 0.05 ? 0 0.05 ? 0.05 vdc 15 ? 0.05 ? 0 0.05 ? 0.05 vdc ?1? level v oh 5.0 4.95 ? 4.95 5.0 ? 4.95 ? vdc v in = 0 or v dd 10 9.95 ? 9.95 10 ? 9.95 ? vdc 15 14.95 ? 14.95 15 ? 14.95 ? vdc input voltage ?0? level (v o = 4.5 or 0.5vdc) v il 5.0 ? 1.5 ? 2.25 1.5 ? 1.5 vdc (v o = 9.0 or 1.0vdc) 10 ? 3.0 ? 4.50 3.0 ? 3.0 vdc (v o = 13.5 or 1.5vdc) 15 ? 4.0 ? 6.75 4.0 ? 4.0 vdc ?1? level (v o = 0.5 or 4.5vdc) v ih 5.0 3.5 ? 3.5 2.75 ? 3.5 ? vdc (v o = 1.0 or 9.0vdc) 10 7.0 ? 7.0 5.50 ? 7.0 ? vdc (v o = 1.5 or 13.5vdc) 15 11.0 ? 11.0 8.25 ? 11.0 ? vdc output drive current source (v oh = 2.5vdc) i oh 5.0 ? 3.0 ? ? 2.4 ? 4.2 ? ? 1.7 ? madc (v oh = 4.6vdc) 5.0 ? 0.64 ? ? 0.51 ? 0.88 ? ? 0.36 ? madc (v oh = 9.5vdc) 10 ? 1.6 ? ? 1.3 ? 2.25 ? ? 0.9 ? madc (v oh = 13.5vdc) 15 ? 4.2 ? ? 3.4 ? 8.8 ? ? 2.4 ? madc sink (v ol = 0.4vdc) i ol 5.0 0.64 ? 0.51 0.88 ? 0.36 ? madc (v ol = 0.5vdc) 10 1.6 ? 1.3 2.25 ? 0.9 ? madc (v ol = 1.5vdc) 15 4.2 ? 3.4 8.8 ? 2.4 ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 0.1 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 ? 0.25 ? 0.0005 0.25 ? 7.5 adc 10 ? 0.5 ? 0.0010 0.5 ? 15 adc 15 ? 1.0 ? 0.0015 1.0 ? 30 adc total supply current (dynamic plus quiescent, per gate, c l = 50pf, note 3, note 4) i t 5.0 i t = (0.3 a/khz) f + i dd /n adc 10 i t = (0.6 a/khz) f + i dd /n adc 15 i t = (0.8 a/khz) f + i dd /n adc note 2. data labeled ?typ? is not to be used for design purposes but is intended as an indication of the device?s potential performance. note 3. the formulas given are for the typical characteristics only at +25 c. note 4. to calculate total supply current at loads other than 50pf: i t (c l ) = i t (50pf) + (c l ? 50) v fk where: i t is in h (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.001 x the number of exercised gates per package.
switching characteristics: (c l = 50pf, t a = +25 c, note 2) parameter symbol v dd vdc min typ max unit output rise time t tlh = (1.35ns/pf) c l + 33ns t tlh 5.0 ? 100 200 ns t tlh = (0.60ns/pf) c l + 20ns 10 ? 50 100 ns t tlh = (0.40ns/pf) c l + 20ns 15 ? 40 80 ns output fall time t thl = (1.35ns/pf) c l + 33ns t thl 5.0 ? 100 200 ns t thl = (0.60ns/pf) c l + 20ns 10 ? 50 100 ns t thl = (0.40ns/pf) c l + 20ns 15 ? 40 80 ns propagation delay time t plh , t phl = (0.90ns/pf) c l + 115ns t plh . t phl 5.0 ? 160 300 ns t plh , t phl = (0.36ns/pf) c l + 47ns 10 ? 65 130 ns t plh , t phl = (0.26ns/pf) c l + 37ns 15 ? 50 100 ns note 2. data labeled ?typ? is not to be used for design purposes but is intended as an indication of the device?s potential performance. note 3. the formulas given are for the typical characteristics only at +25 c. v dd pin connection diagram logic diagram 2 3 1 v dd = pin14 v ss = pin7 6 4 5 9 10 8 13 11 12 h a v ss 1 2 3 4 b j = a + b k = c + d 5 c 6 d 7 14 13 12 11 g m = g + h 10 l = e + f 9 f 8 e
17 14 8 .300 (7.62) .200 (5.08) max .100 (2.45) .099 (2.5) min .785 (19.95) max .600 (15.24)
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